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| KAB0xD100M - TxGP Document Title Multi-Chip Package MEMORY SEC Only MCP MEMORY 64M Bit (8Mx8/4Mx16) Dual Bank NOR Flash / 128M Bit (8Mx16) NAND Flash / 32M Bit (2Mx16) UtRAM Revision History Revision No. History 0.0 0.1 Initial Draft Inserted No ECC condition in NAND Flash * Endurance (1page) : 1,000 Program/Erase Cycles Maximum without ECC * Program Flow (39page) : Excluded "Read Verify" step after programming in this condition Draft Date March 20, 2002 March 28, 2002 Remark Preliminary Preliminary 0.2 March 28, 2002 Preliminary 0.3 June 17, 2002 Final 1.0 1.1 October 15, 2002 June 18, 2003 Final Final 1.11 August 14, 2003 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. -1Revision 1.11 August 2003 KAB0xD100M - TxGP Multi-Chip Package MEMORY FEATURES SEC Only MCP MEMORY GENERAL DESCRIPTION The KAB0xD100M featuring single 3.0V power supply is a Multi Chip Package Memory which combines 64Mbit NOR Flash, 128Mbit NAND Flash and 32Mbit Unit Transistor CMOS RAM. 64Mbit NOR Flash memory is organized as 8M x8 or 4M x16 bit, 128Mbit NAND Flash memory is organized as 8M x16 bit and 32Mbit UtRAM is organized as 2M x16 bit. The memory architecture of NOR Flash memory is designed to divide its memory arrays into 135 blocks and this provides highly flexible erase and program capability. This device is capable of reading data from one bank while programming or erasing in the other bank with dual bank organization. NOR Flash memory performs a program operation in units of 8 bits (Byte) or 16 bits (Word) and erases in units of a block. Single or multiple blocks can be erased. The block erase operation is completed for typically 0.7sec. In 128Mbit NAND Flash a 256-word page program can be typically achieved within 200s and an 8K-word block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. DQ pins serve as the ports for address and data input/output as well as command inputs. The KAB0xD100M is suitable for the memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 80-ball TBGA package. 64M Bit (8Mx8/4Mx16) Dual Bank NOR Flash / 128M Bit (8Mx16) NAND Flash / 32M Bit (2Mx16) UtRAM * Power Supply Voltage : 2.7V~3.1V * Organization - NOR Flash : 8,388,608 x 8 bit / 4,194,304 x 16 bit - NAND Flash : (8M + 256K)bit x 16bit - UtRAM : 2Mbit x 16 bit * Access Time - NOR Flash : 70ns(Max.) - NAND Flash : Random : 10us(Max.), Serial : 50ns(Min.) - UtRAM : 85ns * Power Consumption (typical value) - NOR Flash Read Current : 14mA (@5MHz) Program/Erase Current : 15mA Read while Program or Read while Erase : 35mA Standby Mode/Autosleep Mode : 10A - NAND Flash Read Current : 10mA(@20MHz) Program/Erase Current : 10mA Standby Current : 10A - UtRAM Operating Current : 30mA Standby Current : 80A * NOR Flash Secode(Security Code) Block : Extra 64KB Block * NOR Flash Block Group Protection / Unprotection * NOR Flash Bank Size : 16Mb / 48Mb , 32Mb / 32Mb * NAND Flash Automatic Program and Erase Page Program: (256 + 8)Word, Block Erase: (8K + 256)Word * NAND Flash Fast Write Cycle Time Program time : 200s(Typ.) Block Erase Time : 2ms(Typ.) * Endurance NOR : 100,000 Program/Erase Cycles Minimum NAND : 100,000 Program/Erase Cycles Minimum with ECC : 1,000 Program/Erase Cycles Maximum without ECC * Data Retention : 10 years * Operating Temperature : -25C ~ 85C * Package : 80 - Ball TBGA Type - 8 x 12mm, 0.8 mm pitch BALL DESCRIPTION Ball Name A0 to A20 A-1, A21 DQ0 to DQ7 DQ8 to DQ15 VccR VccF VccU VccQU Vss WE OE CER CEF CSU RESET WP/ACC BYTE Description Address Input Balls (NOR, UtRAM) Address Input Balls (NOR) Data Input/Output Balls (Common) Data Input/Output Balls (Common) Power Supply (NOR) Power Supply (NAND) Power Supply (UtRAM) Data Output Buffer Power (UtRAM) Ground (Common) Write Enable (Common) Output Enable (NOR,UtRAM) Chip Enable (NOR) Chip Enable (NAND) Chip Enable (UtRAM) Hardware Reset (NOR) Hardware Write Protection/Program Acceleration (NOR) Byte Control (NOR) Read/Busy (NOR) Write Protection (NAND) Command Latch Enable(NAND) Address Latch Enable(NAND) Read/Busy (NAND) Output Enable (NAND) Deep Power Down (UtRAM) Upper Byte Enable (UtRAM) Lower Byte Enable (UtRAM) No Connection Do Not Use BALL CONFIGURATION 1 A B C D E F G H J K L M N DNU DNU A6 A5 A4 A3 A1 A0 OE DQ8 DQ0 DNU DNU R/BR A18 A17 CLE ALE WP/ ACC A7 WP CER N.C VccF VccU Vss R/BF A9 A10 2 3 4 5 6 7 8 DNU DNU A12 A13 A14 A15 RESET N.C N.C LB CEF N.C WE A20 A19 RE A2 CSU UB ZZ N.C Vss VccU VccF A11 A8 A21 N.C DQ12 N.C R/BR BYTE A16 WP CLE ALE R/BF RE ZZ UB LB N.C DNU DQ2 DQ11 VccQU DQ9 DQ3 N.C DQ5 DQ14 DQ13 DQ7 DQ15 /A-1 DNU DNU N.C DQ4 DQ1 DQ10 VccR DQ6 80 Ball TBGA , 0.8mm Pitch Top View (Ball Down) SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2Revision 1.11 August 2003 KAB0xD100M - TxGP ORDERING INFORMATION SEC Only MCP MEMORY K A B 0x D 1 0 0 M - T LGP Samsung MCP Memory (3Chip MCP) Device Type B : Dual Bank NOR + NAND + UtRAM Access Time LGP : NOR(70ns) NAND(50ns), UtRAM(85ns) NGP : NOR(80ns) NAND(50ns), UtRAM(85ns) NOR Flash Density, Vcc, & Org. : 64M, Vcc=3.0V, & Org.=x8/x16 : Bank Size(Boot Block) 01 : 16M/48M(Bottom), 02 : 16M/48M(Top) 03 : 32M/32M(Bottom), 04 : 32M/32M(Top) Package T = 80 TBGA Version M = 1st Generation NAND Flash Density (Vcc, Org.) D : 128M (3.0V, x16) DRAM I/F, Density (Vcc, Org.) 0 : NONE UtRAM Density (Vcc, Org.) 1 : 32M (3.0V, x16) SRAM Density (Vcc, Org.) 0 : NONE Figure 1. FUNCTIONAL BLOCK DIAGRAM VccR Vss RESET R/BR A0 to A20 A-1, A21 BYTE CER OE WE I/O Interface & Bank Control Bank1 Address X Dec Bank1 Cell Array Y Dec Bank1 Data-In/Out Bank2 Data-In/Out Latch & Control DQ0 to DQ15 Latch & Control Y Dec Bank2 Address X Dec Bank2 Cell Array Erase Control Program Control High Voltage Gen. X-Buffers Latches & Decoders Y-Gating 2nd half page Register & S/A 128M+4M Bit NAND Flash ARRAY (256 + 8)Word x 32768 1st half page Register & S/A Y-Gating RE ALE CLE WP CEF VccF Vss R/BF Y-Buffers Latches & Decoders DQ0 to DQ15 DQ0 to DQ15 Command Register I/O Buffers & Latches Control Logic & High Voltage Generator Global Buffers Output Driver Clk gen. Precharge circuit. ZZ UB LB CSU VccU VccQU Vss Control logic Data control Row select UtRAM Main Cell Array (2Mb x16) DQ0 to DQ15 I/O Circuit Column select Bottom Boot Block -3- Revision 1.11 August 2003 KAB0xD100M - TxGP Figure 2. NAND Flash ARRAY ORGANIZATION SEC Only MCP MEMORY 1 Block =32 Pages = (8K + 256) Words 32K Pages (=1024 Blocks) Page Register (=256 Bytes) 1 Page = 264 Words 1 Block = 264 Words x 32 Pages = (8K + 256) Words 1 Device = 264 Words x 32Pages x 1024Blocks = 132 Mbits 16 bit 8 Words 256 Words Page Register 256 Words DQ 0 ~ DQ 15 8 Words DQ 0 1st Cycle 2nd Cycle 3rd Cycle A0 A9 A17 DQ 1 A1 A10 A18 DQ 2 A2 A11 A19 DQ 3 A3 A12 A20 DQ 4 A4 A13 A21 DQ 5 A5 A14 A22 DQ 6 A6 A15 A23 DQ 7 A7 A16 *L DQ8 to 15 *L *L *L Column Address Row Address (Page Address) NOTE: Column Address : Starting Address of the Register. * L must be set to "Low" -4- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 02D1 00 KAB 04D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100) Block Size (KB/KW) BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 Bank1 Bank1 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 7FE000H-7FFFFFH 7FC000H-7FDFFFH 7FA000H-7FBFFFH 7F8000H-7F9FFFH 7F6000H-7F7FFFH 7F4000H-7F5FFFH 7F2000H-7F3FFFH 7F0000H-7F1FFFH 7E0000H-7EFFFFH 7D0000H-7DFFFFH 7C0000H-7CFFFFH 7B0000H-7BFFFFH 7A0000H-7AFFFFH 790000H-79FFFFH 780000H-78FFFFH 770000H-77FFFFH 760000H-76FFFFH 750000H-75FFFFH 740000H-74FFFFH 730000H-73FFFFH 720000H-72FFFFH 710000H-71FFFFH 700000H-70FFFFH 6F0000H-6FFFFFH 6E0000H-6EFFFFH 6D0000H-6DFFFFH 6C0000H-6CFFFFH 6B0000H-6BFFFFH 6A0000H-6AFFFFH 690000H-69FFFFH 680000H-68FFFFH 670000H-67FFFFH 660000H-66FFFFH 650000H-65FFFFH 640000H-64FFFFH 630000H-63FFFFH 3FF000H-3FFFFFH 3FE000H-3FEFFFH 3FD000H-3FDFFFH 3FC000H-3FCFFFH 3FB000H-3FBFFFH 3FA000H-3FAFFFH 3F9000H-3F9FFFH 3F8000H-3F8FFFH 3F0000H-3F7FFFH 3E8000H-3EFFFFH 3E0000H-3E7FFFH 3D8000H-3DFFFFH 3D0000H-3D7FFFH 3C8000H-3CFFFFH 3C0000H-3C7FFFH 3B8000H-3BFFFFH 3B0000H-3B7FFFH 3A8000H-3AFFFFH 3A0000H-3A7FFFH 398000H-39FFFFH 390000H-397FFFH 388000H-38FFFFH 380000H-387FFFH 378000H-37FFFFH 370000H-377FFFH 368000H-36FFFFH 360000H-367FFFH 358000H-35FFFFH 350000H-357FFFH 348000H-34FFFFH 340000H-347FFFH 338000H-33FFFFH 330000H-337FFFH 328000H-32FFFFH 320000H-327FFFH 318000H-31FFFFH -5- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 02D1 00 KAB 04D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100) Block Size (KB/KW) BA98 Bank1 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 Bank1 BA84 Bank2 BA83 BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 620000H-62FFFFH 610000H-61FFFFH 600000H-60FFFFH 5F0000H-5FFFFFH 5E0000H-5EFFFFH 5D0000H-5DFFFFH 5C0000H-5CFFFFH 5B0000H-5BFFFFH 5A0000H-5AFFFFH 590000H-59FFFFH 580000H-58FFFFH 570000H-57FFFFH 560000H-56FFFFH 550000H-55FFFFH 540000H-54FFFFH 530000H-53FFFFH 520000H-52FFFFH 510000H-51FFFFH 500000H-50FFFFH 4F0000H-4FFFFFH 4E0000H-4EFFFFH 4D0000H-4DFFFFH 4C0000H-4CFFFFH 4B0000H-4BFFFFH 4A0000H-4AFFFFH 490000H-49FFFFH 480000H-48FFFFH 470000H-47FFFFH 310000H-317FFFH 308000H-30FFFFH 300000H-307FFFH 2F8000H-2FFFFFH 2F0000H-2F7FFFH 2E8000H-2EFFFFH 2E0000H-2E7FFFH 2D8000H-2DFFFFH 2D0000H-2D7FFFH 2C8000H20CFFFFH 2C0000H-2C7FFFH 2B8000H-2BFFFFH 2B0000H-2B7FFFH 2A8000H-2AFFFFH 2A0000H-2A7FFFH 298000H-29FFFFH 290000H-297FFFH 288000H-28FFFFH 280000H-287FFFH 278000H-27FFFFH 270000H-277FFFH 268000H-26FFFFH 260000H-267FFFH 258000H-25FFFFH 250000H-257FFFH 248000H-24FFFFH 240000H-247FFFH 238000H-23FFFFH -6- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 02D1 00 KAB 04D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100) Block Size (KB/KW) BA70 BA69 BA68 Bank1 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 Bank2 BA52 BA51 BA50 Bank2 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 460000H-46FFFFH 450000H-45FFFFH 440000H-44FFFFH 430000H-43FFFFH 420000H-42FFFFH 410000H-41FFFFH 400000H-3FFFFFH 3F0000H-3FFFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2FFFFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH 230000H-237FFFH 228000H-22FFFFH 220000H-227FFFH 218000H-21FFFFH 210000H-217FFFH 208000H-20FFFFH 200000H-207FFFH 1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH -7- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 02D1 00 KAB 04D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 1. NOR Flash Memory Top Boot Block Address (KAB02D100/KAB04D100) Block Size (KB/KW) BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 Bank2 Bank2 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 000000H-007FFFH NOTE: The bank address bits are A21 A20 for KAB02D100, A21 for KAB04D100. Table 2. Secode Block Addresses for Top Boot Devices Device KAB02D100/KAB04D100 Block Address A21-A12 1111111xxx Block Size 64/32 (X8) Address Range 7F0000H-7FFFFFH (X16) Address Range 3F8000H-3FFFFFH -8- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 01D1 00 KAB 03D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 3. NOR Flash Memory Bottom Boot Block Address (KAB01D100/KAB03D100) Block Size (KB/KW) BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 Bank2 Bank2 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 7F0000H-7FFFFFH 7E0000H-7EFFFFH 7D0000H-7DFFFFH 7C0000H-7CFFFFH 7B0000H-7BFFFFH 7A0000H-7AFFFFH 790000H-79FFFFH 780000H-78FFFFH 770000H-77FFFFH 760000H-76FFFFH 750000H-75FFFFH 740000H-74FFFFH 730000H-73FFFFH 720000H-72FFFFH 710000H-71FFFFH 700000H-70FFFFH 6F0000H-6F1FFFH 6E0000H-6EFFFFH 6D0000H-6DFFFFH 6C0000H-6CFFFFH 6B0000H-6BFFFFH 6A0000H-6AFFFFH 690000H-69FFFFH 680000H-68FFFFH 670000H-67FFFFH 660000H-66FFFFH 650000H-65FFFFH 640000H-64FFFFH 630000H-63FFFFH 620000H-62FFFFH 610000H-61FFFFH 600000H-60FFFFH 5F0000H-5FFFFFH 5E0000H-5EFFFFH 5D0000H-5DFFFFH 5C0000H-5CFFFFH 3F8000H-3FFFFFH 3F0000H-3F7FFFH 3E8000H-3EFFFFH 3E0000H-3E7FFFH 3D8000H-3DFFFFH 3D0000H-3D7FFFH 3C8000H-3CFFFFH 3C0000H-3C7FFFH 3B8000H-3BFFFFH 3B0000H-3B7FFFH 3A8000H-3AFFFFH 3A0000H-3A7FFFH 398000H-39FFFFH 390000H-397FFFH 388000H-38FFFFH 380000H-387FFFH 378000H-37FFFFH 370000H-377FFFH 368000H-36FFFFH 360000H-367FFFH 358000H-35FFFFH 350000H-357FFFH 348000H-34FFFFH 340000H-347FFFH 338000H-33FFFFH 330000H-337FFFH 328000H-32FFFFH 320000H-327FFFH 318000H-31FFFFH 310000H-317FFFH 308000H-30FFFFH 300000H-307FFFH 2F8000H-2FFFFFH 2F0000H-2F7FFFH 2E8000H-2EFFFFH 2E0000H-2E7FFFH -9- Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 01D1 00 KAB 03D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 3. NOR Flash Memory Bottom Block Address (KAB01D100/KAB03D100) Block Size (KB/KW) BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 Bank2 Bank2 BA85 BA84 BA83 BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 5B0000H-5BFFFFH 5A0000H-5AFFFFH 590000H-59FFFFH 580000H-58FFFFH 570000H-57FFFFH 560000H-56FFFFH 550000H-55FFFFH 540000H-54FFFFH 530000H-53FFFFH 520000H-52FFFFH 510000H-51FFFFH 500000H-50FFFFH 4F0000H-4FFFFFH 4E0000H-4EFFFFH 4D0000H-4DFFFFH 4C0000H-4CFFFFH 4B0000H-4BFFFFH 4A0000H-4AFFFFH 490000H-49FFFFH 480000H-48FFFFH 470000H-47FFFFH 460000H-46FFFFH 450000H-45FFFFH 440000H-44FFFFH 430000H-43FFFFH 420000H-42FFFFH 410000H-41FFFFH 400000H-40FFFFH 2D8000H-2DFFFFH 2D0000H-2D7FFFH 2C8000H-2CFFFFH 2C0000H-2C7FFFH 2B8000H-2BFFFFH 2B0000H-2B7FFFH 2A8000H-2AFFFFH 2A0000H-2A7FFFH 298000H-29FFFFH 290000H-297FFFH 288000H-28FFFFH 280000H-287FFFH 278000H-27FFFFH 270000H-277FFFH 268000H-26FFFFH 260000H-267FFFH 258000H-25FFFFH 250000H-257FFFH 248000H-24FFFFH 240000H-247FFFH 238000H-23FFFFH 230000H-237FFFH 228000H-22FFFFH 220000H-227FFFH 218000H-21FFFFH 210000H-217FFFH 208000H-20FFFFH 200000H-207FFFH - 10 - Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 01D1 00 KAB 03D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 3. NOR Flash Memory Bottom Boot Block Address (KAB01D100/KAB03D100) Block Size (KB/KW) BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 Bank2 BA54 BA53 Bank1 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 Bank1 BA36 BA35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 3F0000H-3FFFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2F1FFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH - 11 - Revision 1.11 August 2003 KAB0xD100M - TxGP KAB 01D1 00 KAB 03D1 00 Block Address Block A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 SEC Only MCP MEMORY Address Range Byte Mode Word Mode Table 3. NOR Flash Memory Bottom Block Address (KAB01D100/KAB03D100) Block Size (KB/KW) BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 Bank1 Bank1 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 0 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 1 0 1 0 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 00E000H-00FFFFH 00C000H-00DFFFH 00A000H-00BFFFH 008000H-009FFFH 006000H-007FFFH 004000H-005FFFH 002000H-003FFFH 000000H-001FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 007000H-007FFFH 006000H-006FFFH 005000H-005FFFH 004000H-004FFFH 003000H-003FFFH 002000H-002FFFH 001000H-001FFFH 000000H-000FFFH NOTE: The bank address bits are A21 A20 for KAB01D100, A21 for KAB04D100. Table 4. Secode Block Addresses for Bottom Boot Devices Device KAB01D100/KAB03D100 Block Address A21-A12 0000000xxx Block Size 64/32 (X8) Address Range 000000H-00FFFFH (X16) Address Range 000000H-007FFFH - 12 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR FLASH MEMORY COMMAND DEFINITIONS SEC Only MCP MEMORY The NOR Flash Memory operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 5. Note that Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Block Erase Operation is in progress. Table 5. Command Sequences 1st Cycle Command Sequence Addr Read Data Addr Reset Data Autoselect Manufacturer ID (2,3) Autoselect Device Code (2,3) Autoselect Block Group Protect Verify (2,3) Auto Select Secode Block Factory Protect Verify (2,3) Enter Secode Block Region Exit Secode Block Region Program Data Addr Unlock Bypass Data Unlock Bypass Program Unlock Bypass Reset Chip Erase Data Addr Block Erase Data Block Erase Suspend (4, 5) Block Erase Resume CFI Query (6) Data Addr 1 Data Addr 1 Data Addr 1 98H 55H 30H AAH B0H XXXH 6 AAH XXXH 55H 80H AAH 55H 30H Addr 2 Data Addr 2 Data Addr 6 AAH 555H AAAH 55H 2AAH 555H 555H 80H AAAH AAH 555H AAAH 55H 2AAH 555H 10H BA 555H 90H AAAH 00H 2AAH 555H 555H AAAH 555H AAAH 2AAH 555H 555H AAAH A0H XXXH PD XXXH 3 AAH XXXH 55H PA 20H Addr 4 Data Addr 4 Data Addr 4 Data Addr 4 Data Addr 3 Data Addr 4 Data Addr 4 AAH 555H AAAH 55H 2AAH 555H A0H 555H AAAH PD AAH 555H AAAH 55H 2AAH 555H 555H 90H AAAH 00H PA AAH 555H AAAH 55H 2AAH 555H 555H 88H AAAH XXXH AAH 555H AAAH 55H 2AAH 555H 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H AAH 555H AAAH 55H 2AAH 555H DA/ 555H 555H 1 F0H AAAH 2AAH 555H DA/ 555H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H DA/ AAAH 90H AAAH DA/ X00H DA/ X00H 1 RD XXXH Cycle Word RA Byte Word Byte Word Byte Word Byte Word Byte Word Byte 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle ECH DA/ X01H DA/ X02H (See Table 9) BA / X02H BA/ X04H (See Table 9) DA / X03H DA/ X06H (See Table 9) - 13 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOTES: SEC Only MCP MEMORY 1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data DA : Dual Bank Address (A20 - A21), BA : Block Address (A12 - A21), X = Don't care . 2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register. 3. The 4th cycle data of Autoselect mode is output data. The 3rd and 4th cycle bank addresses of Autoselect mode must be same. 4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode. 5. The Erase Suspend command is applicable only to the Block Erase operation. 6. Command is valid when the device is in read mode or Autoselect mode. 7. DQ8 - DQ15 are don't care in command sequence, but RD and PD is excluded. 8. A11 - A21 are also don't care, except for the case of special notice. Table 6. NOR Flash Memory Autoselect Codes DQ8 to DQ15 Description BYTE = VIH Manufacturer ID Device Code KAB02D100 (Top Boot Block) Device Code KAB01D100 (Bottom Boot Block) Device Code KAB04D100 (Top Boot Block) Device Code KAB03D100 (Bottom Boot Block) Block Protection Verification X 22H 22H 22H 22H X BYTE = VIL X X X X X X ECH E0H E2H E1H E3H 01H (Protected), 00H (Unprotected) 80H (Factory locked), 00H (Not factory locked) DQ7 to DQ0 Secode Block Indicator Bit (DQ7) X X NOTES: 1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Address, BA=Block Address, X=Don't care. 2. Secode Block : Security Code Block. - 14 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND FLASH PRODUCT INTRODUCTION SEC Only MCP MEMORY The NAND Flash Memory is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 264 columns. Spare 8 columns are located in 256 to 263 column address. A 264-word data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected like NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by one NAND structures, totaling 8,448 NAND structures of 16 cells. The array organization is shown in Figure 2. Program and read operations are executed on a page basis, while erase operation is executed on a block basis. The memory array consists of 1024 blocks, and a block is separately erasable by 8K-word unit. It indicates that the bit by bit erase operation is prohibited on the NAND Flash Memory. The NAND Flash Memory has addresses multiplexed with lower 8 I/Os. The NAND Flash Memory allows sixteen bit wide data transfer into and out of page registers. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/Os by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except Page Program command and Block Erase command which require two cycles: one cycle for setup and another for execution. The 8M word physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following required command input. In Block Erase operation, however, only two row address cycles are used. Device operations are selected by writing specific commands into command register. Table 7 defines the specific commands of the NAND Flash Memory. Table 7. Command Sets Function Read 1 Read 2 Read ID Reset Page Program Block Erase Read Status 1st. Cycle 00h 50h 90h FFh 80h 60h 70h 2nd. Cycle 10h D0h O O Acceptable Command during Busy Table 8. NOR Flash Operations Table Operation word Read byte Stand-by Output Disable Reset word Write byte Enable Block Group Protect (3) Enable Block Group Unprotect (3) Temporary Block Group L L L X H H H X L L L X L X X X L/H (4) (4) L VccR 0.3V L X L L X H X H H X H X L L X X X H (4) A9 X X X A6 L H X A1 H H X A0 L L X A-1 X X X High-Z X X X DIN DIN DIN X H VID VID VID (2) L/H L/H CER L OE L WE H BYTE H L/H A9 X X X A9 A6 X X X A6 A1 X X X A1 A0 X X X A0 A-1 High-Z High-Z High-Z DIN High-Z High-Z High-Z High-Z DIN DOUT High-Z High-Z High-Z DIN H (2) H L H WP/ ACC A9 A9 A6 A6 A1 A1 A0 A0 DQ15/ A-1 DQ15 DQ8/ DQ14 DOUT DQ0/ DQ7 DOUT RESET H - 15 - Revision 1.11 August 2003 KAB0xD100M - TxGP SEC Only MCP MEMORY NOTES: 1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at VccR0.3 V or Vss0.3 V in the Stand-by mode. 3. Addresses must be composed of the Block address (A12 - A21). The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection". 4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected. Table 9. NAND Flash Operations Table CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CER L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VccF(2) Read Mode Mode Command Input Address Input(3clock) Command Input Address Input(3clock) Write Mode Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by NOTE: 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. Table 10. UtRAM Operations Table CSu H X 1) ZZ H L H H H H H H H H H OE X X 1) 1) WE X X 1) 1) LB X X 1) 1) UB X X 1) 1) I/O0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Deep Power Standby Active Active Active Active Active Active Active Active L L L L L L L L L 1. X = VIL or VIH X1) H H L L L X1) X 1) X1) H H H H H L L L H L X1) L H L L H L H X 1) L H L L H L L X1) - 16 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR FLASH DEVICE OPERATION Byte/Word Mode SEC Only MCP MEMORY If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" , the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB (A1) address pin. Read Mode The NOR Flash memory is controlled by Chip Enable (CER), Output Enable (OE) and Write Enable (WE). When CER and OE are low and WE is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state whenever CER or OE is high. Standby Mode The NOR Flash memory features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CER high (CER = VIH). Refer to the DC characteristics for more details on stand-by modes. Output Disable The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state. Automatic Sleep Mode The NOR Flash Memory features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5A of the current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time. tAA + 50ns Address Outputs Data Data Data Data Data Auto Sleep Mode Data Figure 3. Auto Sleep Mode Operation Autoselect Mode The NOR Flash memory offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. In addition, this mode allows the verification of the status of write protected blocks. The manufacturer and device code can be read via the command register. The Command Sequence is shown in Table 5 and Figure 4. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register. - 17 - Revision 1.11 August 2003 KAB0xD100M - TxGP SEC Only MCP MEMORY WE A21A0(x16)/* A21A-1(x8) DQ15DQ0 555H/ AAAH 2AAH/ 555H 555H/ AAAH 00H/ 00H 01H/ 02H 22E0H or 22E2H AAH 55H 90H ECH F0H Manufacturer Device Code Return to Code (KAB02C100 / KAB01C100) Read Mode NOTE: The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code. Figure 4. Autoselect Operation Write (Program/Erase) Mode The NOR Flash memory executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CER and WE must be low and OE must be high. Addresses are latched on the falling edge of CER or WE (whichever occurs last) and the data are latched on the rising edge of CER or WE (whichever occurs first). The device uses standard microprocessor write timing. Program The NOR Flash memory can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. WE A21A0(x16)/ A21A-1(x8) DQ15-DQ0 R/BR 555H/ AAAH AAH 2AAH/ 555H 55H 555H/ AAAH A0H Program Address Program Data Program Start Figure 5. Program Command Sequence - 18 - Revision 1.11 August 2003 KAB0xD100M - TxGP Unlock Bypass SEC Only MCP MEMORY The NOR Flash memory provides the unlock bypass mode to save its program time. The mode is invoked by the unlock bypass command sequence. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CER pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. WE A21A0(x16)/ A21A-1(x8) DQ15-DQ0 555H/ AAAH AAH 2AAH/ 555H 55H 555H/ AAAH 80H 555H AAAH AAH 2AAH/ 555H 55H 555H/ AAAH 10H Chip Erase Start R/BR Figure 6. Chip Erase Command Sequence Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE or CER, while the Block Erase command is latched on the rising edge of WE or CER. Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Fig 7. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command. - 19 - Revision 1.11 August 2003 KAB0xD100M - TxGP WE SEC Only MCP MEMORY A21A0(x16)/ A21A-1(x8) DQ15-DQ0 555H/ AAAH AAH 2AAH/ 555H 55H 555H/ AAAH 80H 555H/ AAAH AAH 2AAH/ 555H 55H Block Address 30H Block Erase Start R/BR Figure 7. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50s. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20s to suspend the erase operation. But, when the Erase Suspend command is written during the block erase time window (50s) , the device immediately terminates the block erase time window and suspends the erase operation. After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. WE A21A0(x16)/ A21A21A-1(x8) DQ15-DQ0 555H/ AAAH AAH Block Address 30H XXXH XXXH B0H 30H Block Erase Command Sequence Block Erase Start Erase Suspend Erase Resume Figure 8. Erase Suspend/Resume Command Sequence - 20 - Revision 1.11 August 2003 KAB0xD100M - TxGP Read While Write SEC Only MCP MEMORY The NOR Flash memory provides dual bank memory architecture that divides the memory array into two banks. The device is capable of reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-Suspend-Program operation. The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation. Block Group Protection & Unprotection The NOR Flash memory feature hardware block group protection. This feature will disable both program and erase operations in any combination of forty one block groups of memory. Please refer to Tables 12 and 13. The block group protection feature is enabled using programming equipment at the user's site. The device is shipped with all block groups unprotected. This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect operation is executing. The block protection and unprotection can be implemented by the following method. Table 11. Block Group Protection & Unprotection Operation Block Group Protect Block Group Unprotect CER L L OE H H WE L L BYTE X X A9 X X A6 L H A1 H H A0 L L DQ15/ A-1 X X DQ8/ DQ14 X X DQ0/ DQ7 DIN DIN RESET VID VID Address must be inputted to the block group address (A12~A21) during block group protection operation. Please refer to Figure 10 (Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations. Temporary Block Group Unprotect The protected blocks of the NOR Flash memory can be temporarily unprotected by applying high voltage (VID = 8.5V ~ 12.5V) to the RESET ball. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the RESET ball goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC ball is asserted at VIL , the two outermost boot blocks remain protected. VID V = VIH or VIL RESET CER WE Program & Erase operation at Protected Block Figure 9. Temporary Block Group Unprotect Sequence - 21 - Revision 1.11 August 2003 KAB0xD100M - TxGP START COUNT = 1 RESET=VID Wait 1s SEC Only MCP MEMORY First Write Cycle=60h? Yes Yes Block Group Protection ? No No No Temporary Block Group Unprotect Mode Block Protect Algorithm Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 150s Verify Block Group Protect:Write 40H to Block Group address with A6=0, A1=1,A0=0 Read from Block Group address with A6=0, A1=1,A0=0 No COUNT =25? No All Block Groups Protected ? Yes Block Unprotect Algorithm Block Group , i= 0 Block Group Unprotect Write 60H with A6=1,A1=1 A0=0 Wait 15ms Reset COUNT=1 Increment COUNT Increment COUNT Verify Block Group Unprotect:Write 40H to Block Group address with A6=1, A1=1,A0=0 Read from Block Group address with A6=1, A1=1,A0=0 No COUNT =1000? No Set up next Block Group address Data=01h? Data=00h? Yes Yes Device failed Protect another Block Group? No Remove VID from RESET Write RESET command END Yes Yes Device failed Yes Yes Remove VID from RESET Write RESET command END Last Block Group verified ? No NOTE: All blocks must be protected before unprotect operation is executing. Figure 10. Block Group Protection & Unprotection Algorithms - 22 Revision 1.11 August 2003 KAB0xD100M - TxGP Block Address Block Group A21 BGA0 0 A20 0 A19 0 A18 0 A17 0 A16 0 0 BGA1 0 0 0 0 0 1 1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 BGA8 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 BGA15 BGA16 BGA17 BGA18 BGA19 BGA20 BGA21 BGA22 BGA23 BGA24 BGA25 BGA26 BGA27 BGA28 BGA29 BGA30 BGA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 BGA32 1 1 1 1 1 0 1 BGA33 BGA34 BGA35 BGA36 BGA37 BGA38 BGA39 BGA40 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 X A13 X SEC Only MCP MEMORY Table 12. NOR Flash Memory Block Group Address (Top Boot Block) Block A12 X BA0 X BA1 to BA3 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X BA4 to BA7 BA8 to BA11 BA12 to BA15 BA16 to BA19 BA20 to BA23 BA24 to BA27 BA28 to BA31 BA32 to BA35 BA36 to BA39 BA40 to BA43 BA44 to BA47 BA48 to BA51 BA52 to BA55 BA56 to BA59 BA60 to BA63 BA64 to BA67 BA68 to BA71 BA72 to BA75 BA76 to BA79 BA80 to BA83 BA84 to BA87 BA88 to BA91 BA92 to BA95 BA96 to BA99 BA100 to BA103 BA104 to BA107 BA108 to BA111 BA112 to BA115 BA116 to BA119 BA120 to BA123 BA124 to BA126 X 0 1 0 1 0 1 0 1 BA127 BA128 BA129 BA130 BA131 BA132 BA133 BA134 - 23 - Revision 1.11 August 2003 KAB0xD100M - TxGP Block Address Block Group A21 BGA0 BGA1 BGA2 BGA3 BGA4 BGA5 BGA6 BGA7 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 0 BGA8 0 0 0 0 0 1 1 BGA9 BGA10 BGA11 BGA12 BGA13 BGA14 BGA15 BGA16 BGA17 BGA18 BGA19 BGA20 BGA21 BGA22 BGA23 BGA24 BGA25 BGA26 BGA27 BGA28 BGA29 BGA30 BGA31 BGA32 BGA33 BGA34 BGA35 BGA36 BGA37 BGA38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 BGA39 1 1 1 1 1 0 1 BGA40 1 1 1 1 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 SEC Only MCP MEMORY Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 Table 13. NOR Flash Memory Block Group Address (Bottom Boot Block) BA8 to BA10 BA11 to BA14 BA15 to BA18 BA19 to BA22 BA23 to BA26 BA27 to BA30 BA31 to BA34 BA35 to BA38 BA39 to BA42 BA43 to BA46 BA47 to BA50 BA51 to BA54 BA55 to BA58 BA59 to BA62 BA63 to BA66 BA67 to BA70 BA71 to BA74 BA75 to BA78 BA79 to BA82 BA83 to BA86 BA87to BA90 BA91 to BA94 BA95 to BA98 BA99 to BA102 BA103 to BA106 BA107 to BA110 BA111 to BA114 BA115 to BA118 BA119 to BA122 BA123 to BA126 BA127 to BA130 BA131 to BA133 BA134 - 24 - Revision 1.11 August 2003 KAB0xD100M - TxGP Write Protect (WP) SEC Only MCP MEMORY The WP/ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID. The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph). When the WP/ACC ball is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group protection/Unprotection". The write protected blocks can only be read. This is useful method to preserve an important program data. The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or the two blocks containing the highest addresses in a top-boot-congfigured device. (KAB02D100/KAB04D100 : BA133 and BA134, KAB01D100/KAB03D100 : BA0 and BA1) When the WP/ACC ball is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected or unprotected using the method described in "Block Group protection/unprotection". Recommend that the WP/ACC ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Secode(Security Code) Block Region The Secode Block feature provides a NOR Flash memory region to be stored unique and permanent identification code, that is, Electronic Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently fixed at "0" and it is not changed. but once it is protected, there is no procedure to unprotect and modify the Secode Block. The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 8). After the system has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same addresses of the boot blocks (8KBx8). The KAB02D100/KAB04D100 occupies the address of the byte mode 7F0000H to 7FFFFFH (word mode 3F8000H to 3FFFFFH) and the KAB01D100/KAB03D100 type occupies the address of the byte mode 000000H to 00FFFFH (word mode 000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode. Accelerated Program Operation Accelerated program operation reduces the program time through the ACC function. This is one of two functions provided by the WP/ ACC ball. When the WP/ACC ball is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP/ACC ball returns the device to normal operation. Recommend that the WP/ACC ball must not be asserted at VHH except on accelerated program operation, or the device may be damaged. In addition, the WP/ACC ball must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. Software Reset The reset command provides that the device is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode. If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the Erase Suspend state. - 25 - Revision 1.11 August 2003 KAB0xD100M - TxGP Hardware Reset SEC Only MCP MEMORY The NOR Flash memory offers a reset feature by driving the RESET ball to VIL. The RESET ball must be kept low (VIL) for at least 500ns. When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the standby mode after 20us. If a hardware reset occurs during a program operation, the data at that particular location will be lost. Once the RESET ball is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that all the data output balls are tri-stated for the duration of the RESET pulse. The RESET ball may be tied to the system reset ball. If a system reset occurs during the Internal Program and Erase Routine, the device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from the NOR Flash memory. Power-up Protection To avoid initiation of a write cycle during VccR Power-up, RESET low must be asserted during power-up. After RESET goes high, the device is reset to the read mode. Low VccR Write Inhibit To avoid initiation of a write cycle during VccR power-up and power-down, a write cycle is locked out for VccR less than 1.8V. If VccR < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode. Subsequent writes will be ignored until the VccR level is greater than VLKO. It is the users responsibility to ensure that the control balls are logically correct to prevent unintentional writes when VccR is above 1.8V. Write Pulse Glitch Protection Noise pulses of less than 5ns(typical) on CER, OE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited under any one of the following conditions : OE = VIL, CER = VIH or WE = VIH. To initiate a write, CER and WE must be "0", while OE is "1". Commom NOR Flash Memory Interface Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the CFI mode. And then if the system writes the address shown in Table 14, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. - 26 - Revision 1.11 August 2003 KAB0xD100M - TxGP Table 14. Common NOR Flash Memory Interface Code Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH SEC Only MCP MEMORY Addresses (Byte Mode) 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0027H 0036H 0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0017H 0002H 0000H 0000H 0000H 0002H 0007H 0000H 0020H 0000H 007EH 0000H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) VccR Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VccR Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp Min. voltage(00H = no Vpp pin present) Vpp Max. voltage(00H = no Vpp pin present) Typical timeout per single byte/word write 2N us Typical timeout for Min. size buffer write 2 us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms(00H = not supported) Max. timeout for byte/word write 2 times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical(00H = not supported) Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device N N Erase Block Region 1 Information Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information - 27 - Revision 1.11 August 2003 KAB0xD100M - TxGP Table 14. Common NOR Flash Memory Interface Code Description Addresses (Word Mode) 40H 41H 42H 43H 44H 45H SEC Only MCP MEMORY Addresses (Byte Mode) 80H 82H 84H 86H 88H 8AH Data 0050H 0052H 0049H 0030H 0030H 0000H Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 0 = Not Supported, 1 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 04 = K8D1x16U mode Simultaneous Operation (1) 00 = Not Supported, XX = Number of Blocks in Bank2 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00=Not supported, 01=4word page, 02=8word page ACC(Acceleration) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV ACC(Acceleration) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Top/Bottom Boot Block Flag 02H = Bottom Boot , 03H = Top Boot NOTE: 1. The number of blocks in Bank2 is device dependent. KAB02D100/KAB04D100(16Mb/48Mb) = 60h (96blocks) KAB01D100/KAB03D100(32Mb/32Mb ) = 40h (64blocks) 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH 0002H 0001H 0001H 0004H 00XXH 0000H 0000H 0085H 00C5H 000XH - 28 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR FLASH DEVICE STATUS FLAGS SEC Only MCP MEMORY The NOR Flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag via corresponding DQ balls or the R/BR ball. The corresponding DQ balls are DQ7, DQ6, DQ5, DQ3 and DQ2. The status is as follows : Table 15. Hardware Sequence Flags Status Programming Block Erase or Chip Erase Erase Suspend Read In Progress Erase Suspend Read Erase Suspend Program Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle Toggle (Note 1) Data 1 No Toggle (Note 2) No Toggle R/BR 0 0 1 1 0 0 0 0 NOTES: 1. DQ2 will toggle when the device performs successive read operations from the erase suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the Erase Suspend Mode, the status can be detected via the DQ7 ball. If the system tries to read an address which belongs to a block that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. DQ6 : Toggle Bit Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode, an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs to a block that is not being erased, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. DQ5 : Exceed Timing Limits If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. - 29 - Revision 1.11 August 2003 KAB0xD100M - TxGP DQ3 : Block Erase Timer SEC Only MCP MEMORY The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation from the program operation. R/BR : Ready/Busy The NOR Flash memory has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept any read/write or erase operation. When the R/BR pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the NOR Flash memory is placed in an Erase Suspend mode, the R/BR output will be High. For programming, the RY/ BY is valid (R/BR = 0) after the rising edge of the fourth WE pulse in the four write pulse sequence. For Chip Erase, R/BR is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase, R/BR is also valid after the rising edge of the sixth WE pulse. The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required for proper operation. Rp Vcc Vcc (Max.) - VOL (Max.) Rp = Ready / Busy open drain output 2.7 V = 2.1mA + IL IOL + IL where IL is the sum of the input currents of all devices tied to the Ready / Busy pin. Vss Device - 30 - Revision 1.11 August 2003 KAB0xD100M - TxGP SEC Only MCP MEMORY Start Start Yes DQ7 = Data ? No No DQ6 = Toggle ? Yes No DQ5 = 1 ? No DQ5 = 1 ? Yes Yes Yes No DQ7 = Data ? DQ6 = Toggle ? No Yes Fail Pass Fail Pass Figure 11. Data Polling Algorithms Figure 12. Toggle Bit Algorithms Start RESET=VID (Note 1) Perform Erase or Program Operations RESET=VIH Temporary Block Unprotect Completed (Note 2) NOTES: 1. All protected block groups are unprotected. ( If WP/ACC = VIL , the two outermost boot blocks remain protected ) 2. All previously protected block groups are protected once again. Figure 13. Temporary Block Group Unprotect Routine - 31 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND FLASH MEMORY OPERATION PAGE READ SEC Only MCP MEMORY Upon initial device power up, the device status is initially Read1 command(00h) latched. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operation are available : random read, serial page read. The random read mode is enabled when the page address is changed. The 264 words of data within the selected page are transferred to the data registers in less than 10s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out by sequential RE pulse of 50n period cycle. High to low transitions of the RE clock take out the data from the selected column address up to the last column address. Read1 and Read2 commands determine pointer which selects either main area or spare area. The spare area(256 to 263 words) may be selectively accessed by writing the Read2 command. Addresses A0 to A2 set the starting address of spare area while addresses A3 to A7 must be "L". To move the pointer back to the main area, Read1 command(00h) is needed. Figures 16 through 21 show typical sequence and timing for each read operation. Figure 14,15 details the sequence. Figure 14. Read1 Operation CLE CE WE ALE tR R/BF RE DQx 00h Start Add.(3Cycle) Data Output(Sequential) - 32 - Revision 1.11 August 2003 KAB0xD100M - TxGP Figure 15. Read2 Operation CLE CE WE ALE tR R/BF RE DQx 50h (A3 ~ A7 : "L") Start Add.(3Cycle) A0 ~ A2 & A9 ~ A23 SEC Only MCP MEMORY Data Output(Sequential) Spare Field Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it allows multiple partial page program of one word or consecutive words up to 264, in a single page program cycle. The number of consecutive partial page program operation within the same page without intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. Page program cycle consists of a serial data loading(up to 264 words of data) into the page register, and program of loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initiate program process. The internal write controller automatically executes the algorithms and timings necessary for program and verification, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 16). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 16 details the sequence. Figure 16. Program & Read Status Operation R/BF DQx 80h Address & Data Input 10h tPROG 70h DQ0 Pass Fail - 33 - Revision 1.11 August 2003 KAB0xD100M - TxGP BLOCK ERASE SEC Only MCP MEMORY The Erase operation is done on a block(16K Bytes) basis. Block Erase is executed by entering Erase Setup command(60h) and 2 cycle block addresses and Erase Confirm command(D0h). Only address A14 to A23 is valid while A9 to A13 is ignored. This twostep sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition. At the rising edge of WE after erase confirm command input, internal write controller handles erase and erase-verification. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 6 details the sequence. Figure 17. Block Erase Operation R/BF DQx 60h Address Input(2Cycle) Block Add. : A9 ~ A23 Fail tBERS D0h 70h DQ0 Pass READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to command register, a read cycle takes out the content of the Status Register to the I/O pins on the falling edge of CEF or RE. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CEF does not need to be toggled for updated status. Refer to table 16 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. Table 16. Read Status Register Definition DQ # DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8~15 Device Operation Write Protect Not use Reserved for Future Use Status Program / Erase Definition "0" : Successful Program / Erase "1" : Error in Program / Erase "0" "0" "0" "0" "0" "0" : Busy "0" : Protected Don't care "1" : Ready "1" : Not Protected - 34 - Revision 1.11 August 2003 KAB0xD100M - TxGP READ ID SEC Only MCP MEMORY The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (53h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 18 shows the operation sequence. Figure 18. Read ID Operation CLE tCEA CEF WE tAR1 ALE tWHR RE I/Ox tREA 00h Address. 1cycle ECh Maker code 90h 53h Device code RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 17 for device status after reset operation. If the device is already in reset state, new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 19 below. Figure 19. RESET Operation tRST R/BF DQx FFh Table 17. Device Status After Power-up Operation Mode Read 1 After Reset Waiting for next command - 35 - Revision 1.11 August 2003 KAB0xD100M - TxGP READY/BUSY SEC Only MCP MEMORY The device has a R/BF output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/BF pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/BF outputs to be Or-tied. Because pull-up resistor value is related to tr(R/BF) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 20). Its value can be determined by the following guidance. Rp VccR ibusy Ready Vcc R/BF open drain output 0.8V Busy 2.0V tf GND Device tr Figure 20. Rp vs tr ,tf & Rp vs ibusy @ Vcc = 3.3V, Ta = 25C , CL = 100pF 3.3 381 tr,tf [s] 1.65 200n tr 100n 96 4.2 189 1.1 0.825 2m 1m tf 4.2 4.2 4.2 1K 2K 3K Rp(ohm) 4K Rp value guidance VCC(Max.) - VOL(Max.) IOL + IL = 2.7V 8mA + IL Rp = where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 36 - Revision 1.11 August 2003 Ibusy [A] 300n Ibusy 290 3m KAB0xD100M - TxGP Data Protection & Powerup sequence SEC Only MCP MEMORY The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VccF is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 1s is required before internal circuit gets ready for any command sequences as shown in Figure 21. The two step command sequence for program/erase provides additional software protection. Figure 21. AC Waveforms for Power Transition ~ 2.5V VccF High ~ 2.5V WP WE 10s - 37 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Technical Notes Invalid Block(s) SEC Only MCP MEMORY Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding invalid block(s) is so called as the invalid block information. Devices ,regardless of having invalid block(s), have the same quality level because all valid blocks have same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it's bit line and common source line is isolated by a select transistor. The system design must be able to mask out invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction. Identifying Invalid Block(s) All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 1st and 6th word in the spare area. Samsung makes sure that either 1st and 2nd page of every invalid block has non-FFFFh data at the column address of 256 and 261. Since invalid block information is also erasable in most cases, it is impossible to recover the information once it was erased. Therefore, system must be able to recognize the invalid block(s) based on the original invalid block information and create invalid block table via the following suggested flow chart(Figure 22). Any intentional erasure of the original invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Check "FFFFh" at the column address 256 and 261of the 1st and 2nd page in the block Create (or update) Invalid Block(s) Table No Check "FFFFh" ? * Yes No Last Block ? Yes End Figure 22. Flow chart to create invalid block table - 38 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Technical Notes Error in write operation SEC Only MCP MEMORY Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Erase Failure Write Read Program Failure Single Bit Failure (1) Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement Verify ECC -> ECC Correction (2) NOTE: 1. If Program/Erase Cycles is under 1K, Single Bilt Failure do not occure. Therefore there is no need to provide ECC. 2. ECC -> Error Correction Code -> Hamming Code etc. Example) 1bit error correction and 2 bit error detection Figure 24. Flash Program Flow Chart If ECC is used or program/erase cycles are under 1K, this verification operation is not needed. Start Write 00h Write 80h Write Address Write Address Write Data Wait for tR Time Write 10h Verify Data No * Program Error Read Status Register Yes Program Completed I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? No * * Program Error : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Yes - 39 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Technical Notes Figure 24. Flash Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register SEC Only MCP MEMORY DQ 6 = 1 ? or R/B = 1 ? Yes No DQ 0 = 0 ? Yes Erase Completed No * Erase Error * : If erase operation results in an error, map out the failing block and replace it with another block. Figure 25. Block Replacement 1st (n-1)th nth (page) { { Block A 2 1st (n-1)th nth (page) * Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B') * Step3 Then, Copy the 1st ~ (n-1)th data to the same location of the Block 'B'. * Step4 Do not further erase Block 'A' by creating a 'invalid Block' table or other appropriate scheme. Revision 1.11 August 2003 Buffer memory of the controller. Block B 1 - 40 - KAB0xD100M - TxGP NAND Flash Technical Notes Pointer Operation of NAND Flash SEC Only MCP MEMORY Samsung NAND Flash(x16) has two address pointer commands as a substitute for the two most significant column addresses. '00h' command sets the pointer to 'A' area(0~255word), and '50h' command sets the pointer to 'B' area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). '00h' or '50h' is sustained until another address pointer command is inputted. To program data starting from 'A' or 'B' area, '00h' or '50h' command must be inputted before '80h' command is written. A complete read operation prior to '80h' command is not necessary. Table 18. Destination of the pointer Command 00h 50h Pointer position 0 ~ 255 word 256 ~ 263 word Area main array(A) spare array(B) "A" area (00h plane) 256 Word "B" area (50h plane) 8 Word "A" "B" Internal Page Register Pointer select commnad (00h, 50h) Pointer Figure 26. Block Diagram of Pointer Operation (1) Command input sequence for programming 'A' area The address pointer is set to 'A' area(0~255), and sustained Address / Data input 00h 80h 10h 00h 80h Address / Data input 10h 'A','B' area can be programmed. It depends on how many data are inputted. '00h' command can be omitted. (2) Command input sequence for programming 'B' area The address pointer is set to 'B' area(256~263), and sustained Address / Data input 50h 80h 10h 50h 80h Address / Data input 10h Only 'B' area can be programmed. '50h' command can be omitted. - 41 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Technical Notes System Interface Using CE don't-care. SEC Only MCP MEMORY For an easier system interface, CEF may be inactive during data-loading or sequential data-reading as shown below. The internal 264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CEF during the data-loading and reading would provide significant saving in power consumption. Figure 27. Program Operation with CEF don't-care. CLE CEF don't-care CEF WE ALE DQx 80h Start Add.(3Cycle) Data Input Data Input 10h tCS CEF tCH CEF tCEA tREA tWP WE I/O0~7 out RE Figure 28. Read Operation with CEF don't-care. CLE CEF don't-care CEF RE ALE R/BF tR WE DQx 00h Start Add.(3Cycle) Data Output(sequential) - 42 - Revision 1.11 August 2003 KAB0xD100M - TxGP ABSOLUTE MAXIMUM RATINGS Parameter Vcc Voltage on any pin relative to VSS RESET WP/ACC Other Balls Temperature Under Bias Storage Temperature Operating Temperature TBIAS TSTG TA VIN Symbol VccR,VccF,VccU,VccQU Rating -0.2 to Vcc+0.3 -0.2 to 12.5V -0.2 to 12.5V -0.2 to 3.6V -40 to + 125 -65 to + 150 -25 to + 85 SEC Only MCP MEMORY Unit V C NOTE: 1. Minimum DC voltage is -0.2V on input/output balls. During transitions, this level may undershoot to -1.0V for periods <20ns. Maximum DC voltage on input/output balls is VCC+0.3V which, during transitions, may overshoot to VCC+1.0V for periods <20ns. 2. Minimum DC voltage is -0.2V on Reset and WP/ACC balls. During transitions, this level may undershoot to -1.0V for periods <20ns. Maximum DC voltage on on Reset and WP/ACC balls is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to Vss, TA=-25 to 85C) Parameter Supply Voltage Supply Voltage Symbol VccR,VccF,VccU,VccQU VSS Min 2.7 0 Typ. 2.9 0 Max 3.1 0 Unit V V DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) Parameter Input LeaKAge Current Output LeaKAge Current Input Low Voltage Level Input High Voltage Level Output Low Voltage Level Output High Voltage Level Symbol ILI ILO VIL VIH VOL VOH IOL= 2.1mA, Vcc = Vccmin IOH= -1.0mA, Vcc = Vccmin Test Conditions VIN=Vss to Vcc, Vcc=Vccmax VOUT=Vss to Vcc, Vcc=Vccmax, OE=VIH Min -10 -10 -0.3 2.2 2.3 Max 10 10 0.5 Vcc+0.3 0.4 V Unit A A - 43 - Revision 1.11 August 2003 KAB0xD100M - TxGP DC AND OPERATING CHARACTERISTICS Parameter RESET Input Leakage Current WP/ACC Input Leakage Current Active Read Current (1) Active Write Current (2) Read While Program Current (3) Read While Erase Current (3) Program While Erase Suspend Current ACC Accelerated Program Current NOR Flash Standby Current ISB1 Symbol ILIT ILIW ICC1 ICC2 ICC3 ICC4 ICC5 IACC SEC Only MCP MEMORY Test Conditions VccR=VccRmax, RESET=12.5V VccR=VccRmax, WP/ACC=12.5V CER=VIL, OE=VIH CER=VIL, OE=VIH CER=VIL, OE=VIH CER=VIL, OE=VIH CER=VIL, OE=VIH CER=VIL, OE=VIH ACC Ball VccR Ball Min - Typ 14 3 15 25 25 15 5 15 Max 35 35 20 6 30 50 50 35 10 30 Unit A A mA mA mA mA mA mA mA A 5MHz 1MHz VccR=VccRmax, CER=VccR 0.3V, RESET=VccR 0.3V, 10 30 WP/ACC=VccR 0.3V or Vss 0.3V WP/ACC=VccR 0.3V or Vss 0.3V 10 10 30 30 A A Standby Curren During Reset Automatic Sleep Mode Voltage for WP/ACC Block Temporarily Unprotect and Program Acceleration (4) Voltage for Autoselect and Block Protect (4) Low VccR Lock-out Voltage (5) Active Sequential Read Currnt NAND Flash Active Program Current Active Erase Current Stand_by Current(CMOS) ISB2 ISB3 VccR=VccRmax, RESET=Vss0.3V, VIH=VccR 0.3V, VIL=Vss 0.3V, OE=VIL, IOL=IOH=0 VccR= 2.9V 0.2V VccR= 2.9V 0.2V VHH 8.5 - 12.5 V VID VLKO ICC1f ICC2f ICC3f ISB2f ICC1u 8.5 1.8 10 10 10 10 4 12.5 2.5 20 20 20 50 7 V V mA mA mA A mA tRC=50ns,CEF=VIL, IOUT=0mA, VccF=VccFmax VccF=VccFmax VccF=VccFmax CEF=VccF, WP=0V/VccF Cycle time=1s, 100% duty, IIO=0mA, CSU0.2V, ZZVccQU-0.2V, VIN0.2V or VINVccQU-0.2V Cycle time=min, 100% duty, IIO=0mA, CSU=VIL, ZZ=VIH , VIN=VIL or VIH CSuVccQU-0.2V, ZZVccQU-0.2V, Other inputs =0~VccQU ZZ0.2V, Other input =0~VccQU - Operating Current ICC2u UtRAM Stand_by Current(CMOS) Deep Power Down ISB2u ISBD - 30 80 5 35 100 10 mA A A NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz). The read current is typically 14 mA (@ VccR=2.9V , OE at VIH.) 2. ICC active during Internal Routine(program or erase) is in progress. 3. ICC active during Read while Write is in progress. 4. The high voltage ( VHH or VID ) must be used in the range of VccR = 2.9V 0.2V 5. Not 100% tested. 6. Typical values are measured at Vcc = 2.9V, Ta=25C, not 100% tested. - 44 - Revision 1.11 August 2003 KAB0xD100M - TxGP Standby Mode State Machines(UtRAM) CSU=VIH Power On Initial State (Wait 200s) CSU=VIL, UB or/and LB=VIL ZZ=VIH CSU=VIH ZZ=VIH ZZ=VIL Deep Power Down Mode CSU=VIH, ZZ=VIH Standby Mode SEC Only MCP MEMORY Active ZZ=VIL Read Operation Twice Standby Mode Characteristic(UtRAM) Power Mode Standby Deep Power Down Memory Cell Data Valid Invaild Standby Current(A) 100 10 Wait Time(s) 0 200 CAPACITANCE (TA = 25 C, VCC = 2.9V, f = 1.0MHz) Item Input Capacitance Input/Output Capacitance Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 28 30 Unit pF pF NOTE: Capacitance is periodically sampled and not 100% tested. VALID BLOCK OF NAND FLASH MEMORY Parameter Valid Block Number Symbol NVB Min 1004 Typ. Max 1024 Unit Blocks NOTE: 1. The NAND Flash memory may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction. AC TEST CONDITION Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to Vcc 5ns Vcc/2 or VccQU/2 CL = 30pF NOTE: AC test inputs are driven at VccR, VccF or VccU for a logic "1" and 0V for a logic "0". Input timing begins, and output timing ends, at VccR/2, VccF/2 or VccQU/2. Input rise and fall times (10% - 90%)<5ns. Worst case speed condition are when VccR = VccRmin, VccF= VccFmin or VccQU = VccQUmin. Vcc Vcc/2 0V Input & Output Test Point Device Vcc/2 or VccQU/2 CL * CL= 30pF including Scope and Jig Capacitance Input Pulse and Test Point Output Load - 45 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write Parameter Write Cycle Time (1) Address Setup Time Symbol tWC tAS tASO tAH tAHT tDS tDH tOES tOEH1 tOEH2 tCS tCH tWP tWPH Word Byte Word Byte tPGM 70ns Min 70 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 - SEC Only MCP MEMORY 80ns Max Min 80 0 55 45 0 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 50 0 50 20 90 500 500 1 500 200 0 20 20 20 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec s ns ns s ns ns ns s s ns ns ns ns ns Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time CER Setup Time CER Hold Time Write Pulse Width Write Pulse Width High Programming Operation Read (1) Toggle and Data Polling (1) Accelerated Programming Operation Block Erase Operation (2) VccR Set Up Time Write Recovery Time from R/BR RESET High Time Before Read RESET to Power Down Time Program/Erase Valid to R/BR Delay VID Rising and Falling Time RESET Pulse Width RESET Low to R/BR High tACCPGM tBERS tVCS tRB tRH tRPD tBUSY tVID tRP tRRB tRSP tRSTS tRSTW tGHWL tCEPH tOEPH RESET Setup Time for Temporary Unprotect RESET Low Setup Time RESET High to Address Valid Read Recovery Time Before Write CE High during toggling bit polling OE High during toggling bit polling NOTES: 1. Not 100% tested. 2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms. - 46 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CER Controlled Writes Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Output Enable Hold Time WE Setup Time WE Hold Time CER Pulse Width CER Pulse Width High Programming Operation Word Byte Word Byte Read (1) Toggle and Data Polling (1) Symbol tWC tAS tAH tDS tDH tOES tOEH1 tOEH2 tWS tWH tCP tCPH tPGM 70ns Min 70 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 Max - SEC Only MCP MEMORY 80ns Min 80 0 45 35 0 0 0 10 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 0.7(typ.) 25 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns s s s s sec ns Accelerated Programming Operation Block Erase Operation (2) BYTE Switching Low to Output HIGH-Z tACCPGM tBERS tFLQZ NOTES: 1. Not 100% tested. 2.This does not include the preprogramming time. ERASE AND PROGRAM PERFORMANCE Parameter Block Erase Time Chip Erase Time Word Programming Time Byte Programming Time Accelerated Byte/Word Program Time Chip Programming Time Erase/Program Endurance Word Mode Byte Mode Word Mode Byte Mode Limits Min 100,000 Typ 0.7 98 14 9 9 7 59 75 Max 15 330 210 210 150 177 225 Unit sec sec s s s s sec sec cycles Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Minimum 100,000 cycles guaranteed Comments Excludes 00H programming prior to erasure NOTES: 1. 25 C, VccR = 2.9V 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure. - 47 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Read Operations tRC SEC Only MCP MEMORY Address tAA Address Stable CER tOE tDF OE tOEH1 WE tCE tOH Outputs HIGH-Z Output Valid HIGH-Z R/BR HIGH Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CER & OE Disable Time (1) Output Hold Time from Address, CER or OE OE Hold Time NOTE: 1. Not 100% tested. Symbol tRC tAA tCE tOE tDF tOH tOEH1 70ns Min 70 0 0 Max 70 70 25 16 Min 80 0 0 80ns Max 80 80 25 16 - Unit ns ns ns ns ns ns ns - 48 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Hardware Reset/Read Operations SEC Only MCP MEMORY tRC Address tAA Address Stable CER tRH tRP tRH tCE RESET tOH Outputs High-Z Output Valid Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address, CER or OE RESET Pulse Width RESET High Time Before Read Symbol tRC tAA tCE tOH tRP tRH 70ns Min 70 0 500 50 Max 70 70 Min 80 0 500 50 80ns Max 80 80 - Unit ns ns ns ns ns ns - 49 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Alternate WE Controlled Program Operations tAS SEC Only MCP MEMORY Data Polling PA tAH PA tRC Address 555H CER tOES OE tWC tCH tWP tPGM WE tWPH tCS tDH A0H tDS PD tBUSY Status DOUT tRB tCE tOH tOE tDF DATA R/BR NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CER Setup Time CER Hold Time OE Setup Time Write Pulse Width Write Pulse Width High Programming Operation Word Byte Word Byte Symbol tWC tAS tAH tDS tDH tCS tCH tOES tWP tWPH tPGM 70ns Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 70 0 90 0 70 25 16 80 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25 80ns Max - Unit ns ns ns ns ns ns ns ns ns ns us us s s 14(typ.) 9(typ.) 9(typ.) 7(typ.) 80 25 16 - Accelerated Programming Operation Read Cycle Time Chip Enable Access Time Output Enable Time CER & OE Disable Time Output Hold Time from Address, CER or OE Program/Erase Valide to R/BR Delay Recovery Time from R/BR tACCPGM tRC tCE tOE tDF tOH tBUSY tRB ns ns ns ns ns ns ns - 50 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Alternate CER Controlled Program Operations tAS SEC Only MCP MEMORY Data Polling PA tAH PA Address 555H WE tOES OE tWC tCP tPGM CER tWS tDH A0H tDS tCPH DATA PD Status DOUT tBUSY tRB R/BR NOTES: 1. DQ7 is the output of the complement of the data written to the device. 2. DOUT is the output of the data written to the device. 3. PA : Program Address, PD : Program Data 4. The illustration shows the last two cycles of the program command sequence. Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time WE Setup Time WE Hold Time CER Pulse Width CER Pulse Width High Programming Operation Word Byte Word Byte Symbol tWC tAS tAH tDS tDH tOES tWS tWH tCP tCPH tPGM 70ns Min 70 0 45 35 0 0 0 0 35 25 14(typ.) 9(typ.) 9(typ.) 7(typ.) 90 0 90 0 Max Min 80 0 45 35 0 0 0 0 35 25 80ns Max - Unit ns ns ns ns ns ns ns ns ns ns s s s s 14(typ.) 9(typ.) 9(typ.) 7(typ.) - Accelerated Programming Operation Program/Erase Valide to R/BR Delay Recovery Time from R/BR tACCPGM tBUSY tRB ns ns - 51 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Word to Byte Timing Diagram for Read Operation CER OE tCE SEC Only MCP MEMORY BYTE tELFL DQ0-DQ7 DQ8-DQ14 DQ15/A-1 Data Output (DQ8-DQ14) Data Output (DQ15) tFLQZ Data Output (DQ0-DQ7) Address Input (A-1) Byte to Word Timing Diagram for Read Operation CER OE tCE BYTE tELFH Data Output (DQ0-DQ7) Data Output (DQ8-DQ14) Address Input (A-1) tFHQV Data Output (DQ15) DQ0-DQ7 DQ8-DQ14 DQ15/A-1 BYTE Timing Diagram for Write Operation CER The falling edge of the last WE signal WE BYTE tSET (tAS) tHOLD(tAH) Parameter Chip Enable Access Time CER to BYTE Switching Low or High BYTE Switching Low to Output HIGH-Z BYTE Switching High to Output Active Symbol tCE tELFL/tELFH tFLQZ tFHQV 70ns Min Max 70 5 25 25 Min - 80ns Max 80 5 25 25 Unit ns ns ns ns - 52 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Chip/Block Erase Operations tAS SEC Only MCP MEMORY 555H for Chip Erase 2AAH tAH Address 555H 555H 555H 2AAH BA tRC CER tOES OE tWP tWC WE tCS tWPH tDH 10H for Chip Erase 55H 80H AAH 55H 30H DATA AAH tDS R/BR VccR tVCS NOTE: BA : Block Address Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Setup Time CER Setup Time Write Pulse Width Write Pulse Width High Read Cycle Time VccR Set Up Time Symbol tWC tAS tAH tDS tDH tOES tCS tWP tWPH tRC tVCS 70ns Min 70 0 45 35 0 0 0 35 25 70 50 Max Min 80 0 45 35 0 0 0 35 25 80 50 80ns Max - Unit ns ns ns ns ns ns ns ns ns ns s - 53 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Read While Write Operations Read tRC Command tWC DA2 (555H) tAS tAH tAA tCE Read tRC DA1 Command tWC DA2 (PA) Read tRC DA1 SEC Only MCP MEMORY Read tRC DA2 (PA) tAS tAHT Address DA1 CER tOE tCEPH OE tOES tWP tDF tOEH2 WE tDH tDS tDF DQ Valid Output Valid Input (A0H) Valid Output Valid Input (PD) Valid Output Status NOTE: This is an example in the program-case of the Read While Write function. DA1 : Address of Bank1, DA2 : Address of Bank 2 PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out Parameter Write Cycle Time Write Pulse Width Write Pulse Width High Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE Setup Time OE Hold Time CER & OE Disable Time Address Hold Time CER High during toggle bit polling Symbol tWC tWP tWPH tAS tAH tDS tDH tRC tCE tAA tOE tOES tOEH2 tDF tAHT tCEPH 70ns Min 70 35 25 0 45 35 0 70 0 10 0 20 Max 70 70 25 16 Min 80 35 25 0 45 35 0 80 0 10 0 20 80ns Max 80 80 25 16 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - 54 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Data Polling During Internal Routine Operation CER tOE SEC Only MCP MEMORY tDF OE tOEH2 WE tCE tOH DQ7 Data In tPGM or tBERS DQ7 *DQ7 = Valid Data HIGH-Z DQ0-DQ6 Data In Status Data Valid Data HIGH-Z NOTE: *DQ7=Vaild Data (The device has completed the internal operation). R/BR Timing Diagram During Program/Erase Operation CER The rising edge of the last WE signal WE Entire progrming or erase operation R/BR tBUSY Parameter Program/Erase Valid to R/BR Delay Chip Enable Access Time Output Enable Time CER & OE Disable Time Output Hold Time from Address, CER or OE OE Hold Time Symbol tBUSY tCE tOE tDF tOH tOEH2 70ns Min 90 0 10 Max 70 25 16 Min 90 0 10 80ns Max 80 25 16 - Unit ns ns ns ns ns ns - 55 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation tAHT Address* tASO CER tOEH2 WE tOEPH OE tDH DQ6/DQ2 Data In Status Data tCEPH tAHT tAS SEC Only MCP MEMORY tOE Status Data Status Data Array Data Out R/BR NOTE: Address for the write operation must include a bank address (A20~A21) where the data is written. Enter Embedded Erasing Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read Erase Resume Erase Erase Complete WE DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CER NOTE: DQ2 is read from the erase-suspended block. Parameter Output Enable Access Time OE Hold Time Address Hold Time Address Setup Address Setup Time Data Hold Time CER High during toggle bit polling OE High during toggle bit polling Symbol tOE tOEH2 tAHT tASO tAS tDH tCEPH tOEPH 70ns Min 10 0 55 0 0 20 20 Max 25 Min 10 0 55 0 0 20 20 80ns Max 25 - Unit ns ns ns ns ns ns ns ns - 56 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS RESET Timing Diagram R/BR High SEC Only MCP MEMORY CER or OE tRH RESET tRP tREADY Reset Timings NOT during Internal Routine tREADY R/BR tRB CER or OE tRP RESET Reset Timings during Internal Routine Power-up and RESET Timing Diagram tRSTS RESET Vcc Address DATA tAA Parameter RESET Pulse Width RESET Low to Valid Data (During Internal Routine) RESET Low to Valid Data (Not during Internal Routine) RESET High Time Before Read R/BR Recovery Time RESET High to Address Valid RESET Low Set-up Time Symbol tRP tREADY tREADY tRH tRB tRSTW tRSTS 70ns Min 500 50 0 200 500 Max 20 500 Min 500 50 0 200 500 80ns Max 20 500 - Unit ns s ns ns ns ns ns - 57 - Revision 1.11 August 2003 KAB0xD100M - TxGP NOR Flash SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations VID SEC Only MCP MEMORY RESET Vss,VIL, or VIH Vss,VIL, or VIH BGA,A6 A1,A0 Valid Block Group Protect / Unprotect Valid Verify 40H Block Group Protect:150s Block Group UnProtect:15ms Valid DATA 60H 60H Status* 1s CER WE tRB OE tBUSY R/BR NOTES: Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H BGA = Block Group Address (A12 ~ A21) Temporary Block Group Unprotect VID RESET Vss,VIL, or VIH Vss,VIL, or VIH CER WE Program or Erase Command Sequence tVID tRSP tRRB tVID R/BR - 58 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Program/Erase Characteristics(VccF=2.7~3.1V, TA=-25 to 85C) Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol tPROG Nop tBERS Min Typ 200 2 SEC Only MCP MEMORY Max 500 2 3 3 Unit s cycles cycles ms NAND Flash AC Timing Characteristics for Command/Address/Data Input (VccF=2.7~3.1V, TA=-25 to 85C) Parameter CLE Set-up Time CLE Hold Time CEF Setup Time CEF Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH Min 0 10 0 10 25 0 10 20 10 45 15 Max Unit ns ns ns ns ns ns ns ns ns ns ns NAND Flash AC Characteristics for Operation(VccF=2.7~3.1V, TA=-25 to 85C) Parameter Data Transfer from Cell to Register ALE to RE Delay CEF Access Time Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output Hi-Z CEF High to Output Hi-Z RE or CEF High to Output Hold RE High Hold Time Output Hi-Z to RE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCEA tRR tRP tWB tRC tREA tRHZ tCHZ tOH tREH tIR tWHR tRST Min 10 20 25 50 15 15 0 60 Max 10 45 100 30 30 20 5/10/500(1) Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns s NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us - 59 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Command Latch Cycle SEC Only MCP MEMORY CLE tCLS tCS CEF tCLH tCH tWP WE tALS ALE tDS DQx tALH tDH Command NAND Flash Address Latch Cycle tCLS CLE tCS CEF tWC tWC tWP WE tALS ALE tDS DQx tDH tWH tALH tALS tWP tWH tALH tALS tWP tALH tDS tDH tDS tDH A0~A7 A9~A16 A17~A23 - 60 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Input Data Latch Cycle tCLH CLE SEC Only MCP MEMORY tCH CEF tALS ALE tWC tWP WE tDS DQx tWH tDH tWP tDH tWP tDH tDS tDS DIN 0 DIN 1 DIN n NAND Flash Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L) CEF tRC tRP tREA tREH tCHZ* tOH RE tRHZ* tRHZ* tOH DQx tRR R/BF Dout tREA tREA Dout Dout NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. - 61 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND Flash Status Read Cycle tCLS CLE tCLS tCS CEF tCH tWP WE tWHR RE tDS DQx 70h tDH tIR tREA tCEA tCLH SEC Only MCP MEMORY tCHZ* tOH tRHZ* tOH Status Output NAND FLASH READ1 OPERATION(READ ONE PAGE) CLE CEF tWC WE tWB tAR ALE tR RE tRR DQx 00h A0 ~ A7 A9 ~ A16 A17 ~ A23 Dout N Dout N+1 Dout N+2 Dout N+3 tCHZ tOH tRC tRHZ tOH Dout 264 Column Address Page(Row) Address Busy R/BF - 62 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND FLASH READ2 OPERATION(READ ONE PAGE) CLE SEC Only MCP MEMORY CEF WE tWB tR tAR ALE tRR DQx 50h A0 ~ A7 A9 ~ A16 A17 ~ A23 Dout 256+M Dout 256+M+1 RE Dout 264 R/BF M Address A0 ~ A2 : Valid Address A3 ~ A7 : "L" Selected Row 256 8 Start address M NAND FLASH PAGE PROGRAM OPERATION CLE CEF tWC WE tWB ALE tPROG tWC tWC RE Din Din Din 10h 264 N N+1 1 up to 264 Word Data Program Serial Input Command DQx 80h A0 ~ A7 A9 ~ A16 A17 ~ A23 Page(Row) Address 70h Read Status Command DQ0 Sequential Data Column Input Command Address R/BF DQ0=0 Successful Program DQ0=1 Error in Program - 63 - Revision 1.11 August 2003 KAB0xD100M - TxGP NAND FLASH BLOCK ERASE OPERATION(ERASE ONE BLOCK) SEC Only MCP MEMORY CLE CEF tWC WE tWB ALE tBERS RE DQx 60h A9 ~ A16 A17 ~ A23 Page(Row) Address DOh 70h DQ 0 R/BF Auto Block Erase Setup Command Erase Command Busy Read Status Command DQ0=0 Successful Erase DQ0=1 Error in Erase NAND FLASH MANUFACTURE & DEVICE ID READ OPERATION CLE CEF WE ALE tAR RE tREA DQx 90h Read ID Command 00h Address 1st Cycle ECh Maker Code 73h Device Code - 64 - Revision 1.11 August 2003 KAB0xD100M - TxGP UtRAM AC CHARACTERISTICS(VccU=2.7~3.1V, TA=-25 to 85C) SEC Only MCP MEMORY Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 85 10 10 5 0 0 0 5 85 70 0 70 70 60 0 0 35 0 5 85ns1) Max 85 85 40 85 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 1. The limitation in continuous write operation is up to 50 times. If you want to write continuously over 50 times, please refer to the technical note. - 65 - Revision 1.11 August 2003 KAB0xD100M - TxGP UtRAM TIMING DIAGRAMS SEC Only MCP MEMORY TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CSU=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH) tRC1 Address tAA tRC2 CSU tCO tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ tOH Data out High-Z (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2. 4. tOE(max) is met only when OE becomes enable after tAA(max). - 66 - Revision 1.11 August 2003 KAB0xD100M - TxGP TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH) tWC Address tCW(2) CSU tAW tBW tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tDH tWR(4) SEC Only MCP MEMORY UB, LB High-Z tOW TIMING WAVEFORM OF WRITE CYCLE(2)(CSU Controlled, ZZ=VIH) tWC Address CSU tAS(3) UB, LB tCW(2) tAW tBW tWR(4) tWP(1) WE tDW Data in Data Valid tDH Data out High-Z High-Z - 67 - Revision 1.11 August 2003 KAB0xD100M - TxGP TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH) tWC Address tCW(2) CSU tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4) SEC Only MCP MEMORY Data out High-Z High-Z (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CSU and low WE. A write begins when CSU goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CSU goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CSU going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CSU or WE going high. TIMING WAVEFORM OF DEEP POWER DOWN MODE Read Operation Twice or Stay High during 300s 200s ZZ Normal Operation MODE 0.5s Suspend Wake up Normal Operation Deep Power Down Mode CSU (DEEP POWER DOWN MODE) 1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5s suspend period. 2. To return to normal operation, the device needs Wake Up period. 3. Wake Up sequence is just the same as Power up sequences. - 68 - Revision 1.11 August 2003 KAB0xD100M - TxGP TIMING WAVEFORM OF POWER UP(1) SEC Only MCP MEMORY Read Operation Twice 200s VccU(Min) VccU ZZ CSU (POWER UP(1)) 1. After VccU reaches VccU(Min.) following power application, wait 200s with CSU high and then toggle CSU low and commit Read Operation at least twice. Then you get into the normal operation. 2. Read operation should be executed by toggling CSU pin low. 3. The read operation must satisfy the specified tRC. 4. ZZ pin should be kept high during whole power up sequence. TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle) 200s 300s VccU(Min) VccU ZZ CSU (POWER UP(2)) 1. After VccU reaches VccU(Min.) following power application, wait 200s and wait another 300s with CSU high if you don't want to commit dummy read cycle. After total 500s wait, toggle CSU low, then you get into the normal mode. 2. ZZ pin should be kept high during whole power up sequence. - 69 - Revision 1.11 August 2003 KAB0xD100M - TxGP SEC Only MCP MEMORY UtRAM USAGE AND TIMING DESIGN ACHIEVES SRAM SPECIFIC OPERATIONS The UtRAM was designed to work just like an SRAM - without any waits or other overhead for precharging or refreshing its internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides these operations inside with advanced design technology those are not to be seen from outside. Precharging takes place during every access, overlapped between the end of the cycle and the decoding portion of the next cycle. Hiding refresh is more difficult. Every row in every block must be refreshed at least once during the refresh interval to prevent data loss. SAMSUNG provides an internal refresh controller for devices. When all accesses within refresh interval are directed to one macro-cell, as can happen in signal processing applications, a more sophisticated approach is required to hide refresh. The pseudo SRAM is sometimes used on these applications, which requires a memory controller that can hold off accesses when a refresh operation is needed. SAMSUNG's unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power consumption) is that the UtRAM never need to hold off accesses, and indeed it has no hold off signal. The circuitry that gives SAMSUNG this advantage is fairly simple but has not previously been disclosed. TECHNICAL NOTE INTRODUCTION UtRAM is based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the UtRAM unique is that it offers a true SRAM style interface that hides all refresh operations from the memory controller. START WITH A DRAM TECHNOLOGY The key point of UtRAM is its high speed and low power. This high speed comes from the use of many small blocks such as 32Kbits each to create UtRAM arrays. The small blocks have short word lines thus with little capacitance eliminating a major factor of operating current dissipation in conventional DRAM blocks. Each independent macro-cell on a UtRAM device consists of a number of these blocks. Each chip has one or more macro. The address decoding logic is also fast. UtRAM performs a complete read operation in every tRC, but UtRAM needs power up sequence like DRAM. Power Up Sequence and Diagram 1. Apply power. 2. Maintain stable power for a minium 200s with CSU=high. 3. Issue read operation at least 2 times. CSU=VIL, UB or/and LB=VIL ZZ=VIH Active AVOID TIMING Following figures show you an abnormal timing which is not supported on UtRAM and its solution. If your system has a timing which sustains invalid states over 4s at read mode like Figure 29, there are some guide lines for proper operation of UtRAM. When your system has multiple invalid address signals shorter than tRC on the timing shown in Figure 1, UtRAM needs a normal read timing(tRC) during that cycle(Figure 30) or needs to toggle CSU once to 'high' for about 'tRC'(Figure 31). CSU=VIH Power On Initial State (Wait 200s) Read Operation(2 times) Figure 29. Over 4s CSU WE Less than tRC Address Figure 30. Over 4s Put on read operation every 4s CSU WE tRC Address - 70 - Revision 1.11 August 2003 KAB0xD100M - TxGP Figure 31. toggle CSU to high every 4s Over 4s tRC SEC Only MCP MEMORY CSU WE Address Write operation has similar restriction to Read operation. If your system has a timing which sustains invalid states over 4s at write mode and has continuous write signals with length of Min. tWC over 4s like Figure 32, you must toggle WE once to high Figure 32. Over 4s and make it stay high at least for tRC every 4s or toggle CSU once to high for about tRC. CSU tWP WE Address tWC Figure 33. toggle WE to high and make it stay high at least for tRC every 4s Over 4s CSU tWP WE Address tWC tRC Figure 34. Over 4s toggle CSU to high every 4s CSU tWP tRC WE Address tWC - 71 - Revision 1.11 August 2003 KAB0xD100M - TxGP PACKAGE DIMENSION 80-Ball Tape Ball Grid Array Package (measured in millimeters) SEC Only MCP MEMORY Top View Side View Bottom View #A1 INDEX MARK(OPTIONAL) 8.000.10 8.000.10 0.08 MAX (Datum A) A #A1 B C 0.80x12=9.60 (Datum B) 12.000.10 12.000.10 0.450.05 D 0.80 E F G H J 4.80 K L M N 0.320.05 1.300.10 80- 0.450.05 0.20 M A B A 321 B 0.80x7=5.60 87654 0.80 2.80 - 72 - Revision 1.11 August 2003 12.000.10 |
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